Dynamic Random Access Memory: A Survey

The increasing gap between processor speed and main memory latency has accelerated the development of various innovative architectures from dynamic random access memory(DRAM) vendors. We note that recent DRAM innovations have taken place along three dimensions: reduce access latency, develop new interfaces to achieve higher bandwidth, and add simple logic to the DRAM core for application speciic memories, particularly for graphics. The goal of this report is to provide a comprehensive survey of DRAM operations and the recent DRAM architec-tures from a computer system designer's point of view. We also propose certain mechanisms to exploit the on-chip bandwidth of DRAM array to support certain memory bandwidth-intensive operations that are essential to overall system performance. We show that the current DRAM architectures can be extended to perform those operations by simple modiication to the on-chip self testing logic (Built-In Self-Test) circuit on high-density DRAM chips.